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preliminary?subject to change with out notice this document provides electrical specifications , pin assignments, and package diagrams for mac7100 family of microcontro ller devices. for functional ch aracteristics of the family, refer to the mac7100 microcontroller family reference manual (mac7100rm/d). this document contains the following topics: topic page section 1, ?overview? 1 section 2, ?ordering information? 2 section 3, ?electrical characteristics? 3 section 4, ?device pin assignments? 36 section 5, ?mechanical information? 41 1overview the mac7100 family of microc ontrollers (mcus) are member s of a pin-compatible family of 32-bit flash-memory-based devices develo ped specifically for embedded automotive applications. the pin-compatible family concept enables users to select between different memory and peripheral options for scalable designs. all mac7100 family members are composed of a 32-bit central processing unit (arm7tdmi-s), up to 512kbytes of embedded flash eeprom for program storage, up to 32 kbytes of embedded flash for data and/or program storage, and up to 32kbytes of ram. the family is implemented with an enhanced dma (edma) controller to impr ove performance for transfers between memory and many of the on-chip peripherals. the peripheral set includes asynchronous serial communications interfaces (esci), serial peripheral interfa ces (dspi), inter-integrated circuit (i 2 c) bus controllers, flexcan interfaces, an enhan ced modular i/o subsystem (emios), 10-bit analog-to-digital converter (atd) channe ls, general-purpose timers (pit) and two special-purpose timers (rti and swt). the pe ripherals share a large number of general purpose input-output (gpio) pins, all of whic h are bidirectional and available with interrupt capability to trigger wake-up from low-power chip modes. the inclusion of a pll circuit allows power co nsumption and performance to be adjusted to suit operational requirem ents. the operating frequency of de vices in the family is up to a maximum of 50 mhz. the internal data pa ths between the cpu core, edma, memory and peripherals are all 32 bits wide, further impr oving performance for 32 -bit applications. the advance information mac7100ec/d rev. 0.1, 10/2003 mac7100 microcontroller family hardware specifications 32-bit embedded controller division f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice ordering information mac7111 and mac7131 also offer a 16-bit wide exte rnal data bus with 22 address lines. the family of devices is capable of operating over a junction temperature range of -40 c to 150 c. table 1 provides a comparison of members of the ma c7100 family and the availability of peripheral modules on the various devices. 2 ordering information figure 1. order part number example table 1. mac7100 family device derivatives module options mac7101 mac7111 mac7121 mac7131 mac7141 program flash 512kbytes 512kbytes 512kbytes 512kbytes 512kbytes data flash 32kbytes 32kbytes 32kbytes 32kbytes 32kbytes sram 32kbytes 32kbytes 32kbytes 32kbytes 32kbytes external bus no yes no yes no atd modules 2 1 1 2 1 can modules 4 4 4 4 2 esci modules 4 4 4 4 2 dspi modules 2 2 2 2 2 i 2 c modules 1 1 1 1 1 emios module 16 channels, 16-bit 16 channels, 16-bit 16 channels, 16-bit 16 channels, 16-bit 16 channels, 16-bit timer module 10 channels, 24-bit 10 channels, 24-bit 10 channels, 24-bit 10 channels, 24-bit 10 channels, 24-bit gpio pins (max.) 111 111 84 127 71 package 144 lqfp 144 lqfp 112 lqfp 208 map bga 100 lqfp m ac 7 1 0 1 c pv 50 xx mc status core code core number generation / family package option device number temperature range package identifier speed (mhz) optional package identifiers temperature option c = ?40 c to 85 c v = ?40 c to 105 c m = ?40 c to 125 c package option fu = 100 qfp pv = 112 / 144 lqfp vf = 208 map bga f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mac7100 microcontroller family hardware specifications 3 preliminary?subject to change without notice electrical characteristics 3 electrical characteristics this section contains electrical information for mac7100 family microcontrollers. the information is preliminary and subject to change without notice. mac7100 family devices are specified and tested over the 5 v and 3.3 v ranges. for operation at any voltage within that range, the 3.3 v specifications generally apply. ho wever, no production testing is done to verify operation at interm ediate supply voltage levels. 3.1 parameter classification the electrical parameters shown in this appendix are derived by various methods. to provide a better understanding to the designer, the fo llowing classification is used. parame ters are tagged accordingly in in the column labeled ?c? of the pa rametric tables, as appropriate. 3.2 absolute maximum ratings absolute maximum ratings are stress ratings only. fu nctional operation outside these maximums is not guaranteed. stress beyond these limits may affect reliability or cause perman ent damage to the device. mac7100 family devices contain circuitry protectin g against damage due to high static voltage or electrical fields; however, it is advised that normal pr ecautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. relia bility of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either v ss 5 or v dd 5). table 2. parametric value classification p parameters guaranteed during production testing on each individual device. c parameters derived by the design characterizati on and by measuring a statistically relevant sample size across process variations. t parameters derived by design characterization on a small sample size from typical devices under typical conditions (unless otherwise not ed). all values shown in the typical column are within this classification, even if not so tagged. d parameters derived mainly from simulations. table 3. absolute maximum ratings num rating symbol min max unit a1 i/o, regulator and analog supply voltage v dd 5?0.3 +6.0v a2 digital logic supply voltage 1 v dd 2.5 ?0.3 +3.0 v a3 pll supply voltage 1 v dd pll ?0.3 +3.0 v a4 atd supply voltage v dd a?0.3 +6.5v a5 analog reference v rh, v rl ?0.3 +6.0 v a6 voltage difference v dd x to v dd a ? vddx ?0.3 +0.3 v a7 voltage difference v ss x to v ss a ? vssx ?0.3 +0.3 v a8 voltage difference v rh ? v rl v rh ? v rl ?0.3 +6.5 v a9 voltage difference v dd a ? v rh v dd a ? v rh ?6.5 +6.5 v a10 digital i/o input voltage v in ?0.3 +6.0 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.3 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. duri ng the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model. a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parame tric and functional testing is pe rformed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise. a11 xfc, extal, xtal inputs v ilv ?0.3 +3.0 v a12 test input v test ?0.3 +10.0 v instantaneous maximum current 2 a13 single pin limit for xfc, extal, xtal 3 i dl ?25 +25 ma a14 single pin limit for all digital i/o pins 4 i d ?25 +25 ma a15 single pin limit for all analog input pins 4 i da ?25 +25 ma a16 single pin limit for test 5 i dt ?0.25 0 ma a17 storage temperature range t stg ?65 +155 c 1 the device contains an internal voltage regulator to ge nerate the logic and pll supply from the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. 2 input must be current limited to the value specified. to de termine the value of the requ ired current-limiting resistor, calculate resistance values using v posclamp = v dd a + 0.3 v and v negclamp = ?0.3 v, then use the larger of the calculated values. 3 these pins are internally clamped to v ss pll and v dd pll. 4 all i/o pins are internally clamped to v ss x and v dd x, v ss r and v dd r or v ss a and v dd a. 5 this pin is clamped low to v ss x, but not clamped high, and mu st be tied low in applications. table 4. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulses per pin positive negative ?? 3 3 machine series resistance r1 0 ohm storage capacitance c 200 pf number of pulse per pin positive negative ?? 3 3 latch-up minimum input voltage limit ?2.5 v maximum input voltage limit 7.5 v table 3. absolute maximum ratings (continued) num rating symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mac7100 microcontroller family hardware specifications 5 preliminary?subject to change without notice electrical characteristics 3.4 operating conditions unless otherwise noted, the following conditions apply to all parametric data. refer to the temperature rating of the device (c, v, m) with respect to ambient temperature (t a ) and junction temperature (t j ). for power dissipation calculations refer to section 3.5, ?power dissipation and th ermal characteristics.? table 5. esd and latch-up protection characteristics num c rating symbol min max unit b1 c human body model (hbm) v hbm 2000 ? v b2 c machine model (mm) v mm 200 ? v b3 c charge device model (cdm) v cdm 500 ? v b4 c latch-up current at t a = 125 c positive negative i lat +100 ?100 ? ma b5 c latch-up current at t a = 27 c positive negative i lat +200 ?200 ?ma table 6. mac7100 family device operating conditions num rating symbol min typ max unit c1 i/o, regulator and analog supply voltage v dd 5 4.5 5 5.5 v c2 digital logic supply voltage 1 1 the device contains an internal voltage regulator to ge nerate the logic and pll supply from the i/o supply. the absolute maximum rating s apply when this regulator is disabled and the device is powered from an external source. v dd 2.5 2.35 2.5 2.75 v c3 pll supply voltage 1 v dd pll 2.35 2.5 2.75 v c4 voltage difference v dd x to v dd a ? vdd x ?0.1 0 0.1 v c5 voltage difference v ss x to v ss a ? vss x ?0.1 0 0.1 v c6 oscillator frequency f osc 0.5 ? 16 mhz c7 bus frequency f bus 0.5 ? 50 mhz c8a mac7100 c operating junction temperature range 2 t j ?40 ? 110 c c8b operating ambient temperature range 2 2 please refer to section 3.5, ?power dissipation and therma l characteristics,? for more details about the relation between ambient temperature t a and device junction temperature t j . t a ?40 25 85 c c9a mac7100 v operating junction temperature range 2 t j ?40 ? 130 c c9b operating ambient temperature range 2 t a ?4025105 c c10a mac7100 m operating junction temperature range 2 t j ?40 ? 150 c c10b operating ambient temperature range 2 t a ?4025125 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.4.1 5 v i/o pins the i/o pins operate at a nominal level of 5 v. this class of pins is comprised of the clocks, control and general purpose/peripheral pins. the internal structure of these pins is identical; however, some functionality may be disabled (for example, for analog inputs the output drivers, pull-up/down resistors are permanently disabled). 3.4.2 oscillator pins the pins xfc, extal, xtal are dedicated to the oscillator and operate at a nominal level of 2.5 v. 3.5 power dissipation and thermal characteristics power dissipation and thermal characteristics are closel y related. the user must assure that the maximum operating junction temperature is not exceeded. note that the jedec specifi cation reserves the symbol r ja or ja (theta-ja) strictly for junction-to- ambient thermal resistance on a 1s test bo ard in natural convection environment. r jma or jma (theta-jma) will be used for both ju nction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test bo ards. it is anticipated that the generic name, ja , will continue to be commonly used. the average chip-junction temperature (t j ) in c is obtained from: the total power dissipation is calculated from: two cases for p io , with the internal voltage regulator en abled and disabled, must be considered: 1. internal voltage regulator disabled: p io is the sum of all output current s on i/o ports associated with v dd x and v dd r. or 2. internal voltage regulator enabled: i dd r is the current shown in table 12 and not the overall current flowing into v dd r, which additionally contains the current flowing in to the external loads with output high. t j t a ja () + = t j junction temperature ( c) = t a ambient temperature ( c) = p d total chip power dissipation (w) = ja package thermal resistance ( c/w) = p d p int p io + = p int chip internal power dissipation (w) = p int i dd v dd () i dd pll v dd pll () i dd av dd a () ++ = p io r dson i i io i () 2 ? = r dson v ol i ol --------- - (for outputs driven low) = r dson v dd 5v oh ? i ol ------------------------------- (for outputs driven high) = p int i dd rv dd r () i dd av dd a () + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mac7100 microcontroller family hardware specifications 7 preliminary?subject to change without notice electrical characteristics 3.5.1 power dissipation simulation details comments: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the boar d, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with t he single layer board (jesd51-3) horizontal. 3. per jedec jesd51-6 with the board (jesd51-7) horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temper ature is measured on the top surface of the board at the cent er lead. for fused lead packages, the adjacent lead is used. 5. thermal resistance between the die and the case top surface as measured by the cold plate me thod (mil spec-883 method 1012.1) . 6. thermal characterization parameter indicating the temperature difference between package top and junction temperature per jed ec jesd51-2. when greek letters are not available, the ther mal characterization paramete r is written as psi-jt. table 7. thermal resistance for 100 lead 14x14 mm lqfp, 0.5 mm pitch 1 1 100 lqfp, case outline: 983?02 rating value unit comments junction to ambient (natural convection) single layer board (1s) r ja 44 c/w 1, 2 junction to ambient (natural convection) four layer board (2s2p) r jma 34 c/w 1, 3 junction to ambient (@ 200 f t./min.) single layer board (1s) r jma 37 c/w 1, 3 junction to ambient (@ 200 ft./min.) four layer board (2s2p) r jma 29 c/w 1, 3 junction to board r jb 18 c/w 4 junction to case r jc 7c/w 5 junction to package top natural convection jt 2c/w 6 table 8. thermal resistance for 112 lead 20x20 mm lqfp, 0.65 mm pitch 1 1 112 lqfp, case outline: 987?01 rating value unit comments junction to ambient (natural convection) single layer board (1s) r ja 42 c/w 1, 2 junction to ambient (natural convection) four layer board (2s2p) r jma 34 c/w 1, 3 junction to ambient (@ 200 ft./min.) single layer board (1s) r jma 35 c/w 1, 3 junction to ambient (@ 200 ft./min.) four layer board (2s2p) r jma 30 c/w 1, 3 junction to board r jb 22 c/w 4 junction to case r jc 7c/w 5 junction to package top natural convection jt 2c/w 6 table 9. thermal resistance for 144 lead 20x20 mm lqfp, 0.5 mm pitch 1 1 144 lqfp, case outline: 918?03 rating value unit comments junction to ambient (natural convection) single layer board (1s) r ja 42 c/w 1, 2 junction to ambient (natural convection) four layer board (2s2p) r jma 34 c/w 1, 3 junction to ambient (@ 200 ft./min.) single layer board (1s) r jma 35 c/w 1, 3 junction to ambient (@ 200 ft./min.) four layer board (2s2p) r jma 30 c/w 1, 3 junction to board r jb 22 c/w 4 junction to case r jc 7c/w 5 junction to package top natural convection jt 2c/w 6 table 10. thermal resistance for 208 lead 17x17 mm map, 1.0 mm pitch 1 1 208 map bga, case outline: 1159a-01 rating value unit comments junction to ambient (natural convection) single layer board (1s) r ja 46 c/w 1, 2 junction to ambient (natural convection) four layer board (2s2p) r jma 29 c/w 1, 3 junction to ambient (@ 200 ft./min.) single layer board (1s) r jma 38 c/w 1, 3 junction to ambient (@ 200 ft./min.) four layer board (2s2p) r jma 26 c/w 1, 3 junction to board r jb 19 c/w 4 junction to case r jc 7c/w 5 junction to package top natural convection jt 2c/w 6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.6 power supply the mac7100 family utilizes several pi ns to supply power to the oscilla tor, pll, digital core, i/o ports and atd. in the context of this section, v dd 5 is used for v dd a, v dd r or v dd x; v ss 5 is used for v ss a, v ss r or v ss x unless otherwise noted. i dd 5 denotes the sum of the cu rrents flowing into the v dd a, v dd x, and v dd r. v dd is used for v dd 2.5, and v dd pll, v ss is used for v ss 2.5 and v ss pll. i dd is used for the sum of the currents flowing into v dd 2.5 and v dd pll. 3.6.1 current injection the power supply must mainta in regulation within the v dd 5 or v dd 2.5 operating range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd 5) is greater than i dd 5, the injection current may flow out of v dd 5 and could result in th e external power supply going out of regulation. it is import ant to ensure that the external v dd 5 load will shunt current greater than the maximum injection current. the gr eatest risk will be when the mcu is consuming very little power (for example, if no system clock is present, or if the clock rate is very low). 3.6.2 power supply pins the v dd r ? v ss r pair supplies the internal voltage regulator. the v dd a ? v ss a pair supplies the a/d converter and the reference circuit of the internal voltage regulator. the v dd x ? v ss x pair supplies the i/o pins. v dd pll ? v ss pll pair supplies the oscillator and pll. all v dd x pins are internally connected by metal. all v ss x pins are internally co nnected by metal. all v ss 2.5 pins are internally connected by metal. v dd a, v dd x and v dd r as well as v ss a, v ss x and v ss r are connected by anti-parallel diodes for esd protection. 3.6.3 supply currents all current measurements are withou t output loads. unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 40mhz bu s frequency using a 4mhz oscillator in low power mode. production tes ting is performed using a square wave signal at the extal input. in expanded modes, the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of th ose signals. no generally applicable numbers can be given. a good estimate is to take the single chip currents and add the currents due to th e external loads. table 11. power dissipation 1/8 simulation model packaging parameters component conductivity mold compound 0.9 w/m k leadframe (copper) 263 w/m k die attach 1.7 w/m k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mac7100 microcontroller family hardware specifications 9 preliminary?subject to change without notice electrical characteristics table 12. supply current characteristics num c rating symbol typ max unit d1a c run supply current single chip core ?40 c 2 i dd r core ? 1 1 at the time of publication, this value is yet to be determined, and will be supplied when device characterization is complete. ? 1 ma 25 c 2 ? 1 ? 1 ma 85 c 2 2 85 c, 105 c, and 125 c refer to the "c", "v", and "m" temperature options, respectively. ? 1 ? 1 ma 105 c 2 ? 1 ? 1 ma 125 c 2 ? 1 ? 1 ma d1b c regulator (if enabled) ?40 c 2 i dd r reg ? 1 ? 1 ma 25 c 2 ? 1 ? 1 ma 85 c 2 ? 1 ? 1 ma 105 c 2 ? 1 ? 1 ma 125 c 2 ? 1 ? 1 ma d1c c pins ?40 c 2 i dd r pins ? 1 ? 1 ma 25 c 2 ? 1 ? 1 ma 85 c 2 ? 1 ? 1 ma 105 c 2 ? 1 ? 1 ma 125 c 2 ? 1 ? 1 ma d2 c doze supply current run doze pseudo stop d3a c psuedo stop current pll on core ?40 c 2 i dd ps core ? 1 ? 1 a 25 c 2 ? 1 ? 1 a 85 c 2 ? 1 ? 1 a 105 c 2 ? 1 ? 1 a 125 c 2 ? 1 ? 1 a d3b c regulator ?40 c 2 i dd ps reg ? 1 ? 1 a 25 c 2 278 / 327 3 3 rti disabled / enabled. ? 1 a 85 c 2 ? 1 ? 1 a 105 c 2 ? 1 ? 1 a 125 c 2 ? 1 ? 1 a d3c c pins ?40 c 2 i dd ps pins ? 1 ? 1 a 25 c 2 4 / 5 3 ? 1 a 85 c 2 ? 1 ? 1 a 105 c 2 ? 1 ? 1 a 125 c 2 ? 1 ? 1 a d4a c stop current t j = t a assumed core ?40 c 2 i dd s core ? 1 ? 1 a 25 c 2 ? 1 ? 1 a 85 c 2 ? 1 ? 1 a 105 c 2 ? 1 ? 1 a 125 c 2 ? 1 ? 1 a d4b c regulator ?40 c 2 i dd s reg ? 1 ? 1 a 25 c 2 68 ? 1 a 85 c 2 ? 1 ? 1 a 105 c 2 ? 1 ? 1 a 125 c 2 ? 1 ? 1 a d4c c pins ?40 c 2 i dd s pins ? 1 ? 1 a 25 c 2 4? 1 a 85 c 2 ? 1 ? 1 a 105 c 2 ? 1 ? 1 a 125 c 2 ? 1 ? 1 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.6.4 voltage regulator characteristics table 13. vreg operating conditions num c characteristic symbol min typical max unit e1 p input voltages v vddra 2.97 ? 5.5 v e2 p regulator current reduced power mode shutdown mode i reg ? ? tbd tbd 50 40 a a e3 p output voltage core full performance mode reduced power mode shutdown mode v dd 2.45 1.60 ? 2.5 2.5 ? 1 1 high impedance output. 2.75 2.75 ? v v v e4 p output voltage pll full performance mode reduced power mode 2 reduced power mode 3 shutdown mode 2 current i dd pll = 1ma (low power oscillator). 3 current i dd pll = 3ma (standard oscillator). v dd pll 2.35 2.00 1.60 ? 2.5 2.5 2.5 ? 1 2.75 2.75 2.75 ? v v v v e5 p low voltage interrupt 4 assert level deassert level 4 monitors v dd a, active only in full performance mode. indicated i/o and atd performance degradation due to low supply voltage. v lvia v lvid 4.10 4.25 4.37 4.52 4.66 4.77 v v e6 p low voltage reset 5 assert level 5 monitors v dd 2.5, active only in full performance mode. on ly por is active in reduced performance mode. v lvra 2.25 2.35 ? v e7 p power on reset 6 assert level deassert level 6 monitors v dd 2.5, active in all modes. v pora v pord 0.97 ? ? ? ? 2.05 v v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mac7100 microcontroller family hardware specifications 11 preliminary?subject to change without notice electrical characteristics 3.6.5 chip power up and voltage drops the vreg sub-modules lvi (low vol tage interrupt), por (power on reset) and lvr (low voltage reset) handle chip power-up or drops of the supply voltage. refer to figure 2. figure 2. vreg chip power-up and voltage drops 3.6.6 output loads the on-chip voltage regu lator is intended to supply the internal logic and oscilla tor circuits. no external dc load is allowed. capacitive loads ar e specified in table 14. capacitors with x7r dielectricum are required. table 14. vreg recommended load capacitances rating symbol min typ max unit load capacitance on each v dd 2.5 pin c lvdd 200 440 12000 nf load capacitance on v dd pll pin c lvddfcpll 90 220 5000 nf lvi disabled due to lvr v lvid v lvrd lvr por lvi v pord v lvra v lvia time lvi enabled v dd a v dd 2.5 v o l tage note: not to scale. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.7 i/o characteristics this section describes the characteristics of all i/o pins in both 3.3 v and 5 v operating conditions. all parameters are not always applicable; for exampl e, not all pins feature pull up/down resistances. table 15. 5 v i/o characteristics conditions shown in table 6 unless otherwise noted num c rating symbol min typ max unit f1a p input high voltage v ih 0.65 v dd 5 ?? v f1b t input high voltage v ih ??v dd 5+ 0.3 v f2a p input low voltage v il ? ? 0.35 v dd 5 v f2b t input low voltage v il v ss 5 ? 0.3 ?? v f3 c input hysteresis v hys ?250?mv f4 p input leakage current (pins in high impedance input mode) 1 v in = v dd 5 or v ss 5 1 maximum leakage current occurs at ma ximum operating temperature. current decreases by approximately one-half for each 8c to 12c in the temperature range from 50c to 125c. i in tbd ? tbd a f5 p output high voltage (pins in output mode) partial drive i oh = ?2ma full drive i oh = ?10ma v oh v dd 5 ? 0.8 ?? v f6 p output low voltage (pins in output mode) partial drive i ol = +2ma full drive i ol = +10ma v ol ??0.8v f7 p internal pull up device current, tested at v il max. i pul ? ? ?130 a f8 p internal pull up device current, tested at v ih min. i puh ?10 ? ? a f9 p internal pull down device current, tested at v ih min. i pdh ??130 a f10 p internal pull down device current, tested at v il max. i pdl 10 ? ? a f11 d input capacitance c in ?6?pf f12 t injection current 2 single pin limit total device limit. sum of all injected currents 2 refer to section 3.6.1, ?current injection,? for more details i ics i icp ?2.5 ?25 ? 2.5 25 a f13 p port interrupt input pulse filtered 3 3 parameter only applies in stop or pseudo stop mode. t pulse ?? 3 s f14 p port interrupt input pulse passed 3 t pulse 10 ? ? s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mac7100 microcontroller family hardware specifications 13 preliminary?subject to change without notice table 16. 3.3 v i/o characteristics conditions shown in table 6, with v dd x = 3.3 v 10% and a temperature maximum of +140 c unless otherwise noted. num c rating symbol min typ max unit g1a p input high voltage v ih 0.65 v dd 5 ?? v g1b t input high voltage v ih ??v dd 5 + 0.3 v g2a p input low voltage v il ? ? 0.35 v dd 5 v g2b t input low voltage v il v ss 5 ? 0.3 ?? v g3 c input hysteresis v hys ?250?mv g4 p input leakage current (pins in high impedance input mode) 1 v in = v dd 5 or v ss 5 1 maximum leakage current occurs at ma ximum operating temperature. current decreases by approximately one-half for each 8c to 12c in the temperature range from 50c to 125c. i in tbd ? tbd a g5 p output high voltage (pins in output mode) partial drive i oh = ?0.75ma full drive i oh = ?4.5ma v oh v dd 5 ? 0.4 ?? v g6 p output low voltage (pins in output mode) partial drive i ol = +0.9ma full drive i ol = +5.5ma v ol ??0.4v g7 p internal pull up device current, tested at v il max. i pul ? ? ?60 a g8 p internal pull up device current, tested at v ih min. i puh ?6 ? ? a g9 p internal pull down device current, tested at v ih min. i pdh ??60 a g10 p internal pull down device current, tested at v il max. i pdl 6?? a g11 d input capacitance c in ?6?pf g12 t injection current 2 single pin limit total device limit. sum of all injected currents 2 refer to section 3.6.1, ?current injection,? for more details i ics i icp ?2.5 ?25 ? 2.5 25 a g13 p port interrupt input pulse filtered 3 3 parameter only applies in stop or pseudo stop mode. t pulse ?? 3 s g14 p port interrupt input pulse passed 3 t pulse 10 ? ? s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.8 clock and reset generator electrical characteristics this section describes the electrical characteristics for the oscillator, ph ase-locked loop, clock monitor and reset generator. 3.8.1 oscillator characteristics the mac7100 family features an internal low power lo op controlled pierce oscill ator and a full swing pierce oscillator/external clock mode. the selection of loop controlled pierce oscillator or full swing pierce oscillator/external clock depends on the level of the xclks signal at the rising edge of the reset signal. before asserting the oscillator to the internal syst em clock distribution subsystem, the quality of the oscillation is checked for each start from ei ther power on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode after por or stop if a proper oscillation is not detected. the quality check also determi nes the minimum oscillator start-up time t uposc . the device also features a clock monitor. a clock monitor failure is as serted if the frequency of the incoming clock signal is below the clock monitor assert frequency f cmfa . table 17. oscillator characteristics num c rating symbol min typ max unit h1a c crystal oscillator range (loop controlled pierce) f osc 4.0 ? 16 mhz h1b c crystal oscillator range (full swing pierce) 1, 2 1 depending on the crystal; a damping series resistor might be necessary 2 xclks negated during reset f osc 0.5 ? 40 mhz h2 p startup current i osc 100 ? ? a h3 c oscillator start-up time (loop controlled pierce) t uposc ?tbd 3 3 f osc = 4 mhz, c = 22 pf. 50 4 4 maximum value is for extreme cases using high q, low frequency crystals ms h4 d clock quality check time-out t cqout 0.45 ? 2.5 s h5 p clock monitor failure assert frequency f cmfa 50 100 200 khz h6 p external square wave input frequency 2 f ext 0.5 ? 40 mhz h7 d external square wave pulse width low t extl 9.5 ? ? ns h8 d external square wave pulse width high t exth 9.5 ? ? ns h9 d external square wave rise time t extr ?? 1ns h10 d external square wave fall time t extf ?? 1ns h11 d input capacitance (extal, xtal pins) c in ?7?pf h12 c extal pin dc operating bias in loop controlled mode v dcbias ?tbd?v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
15 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.8.2 pll filter characteristics the oscillator provides the reference clock for the pll. the voltage controlled oscillator (vco) of the pll is also the system cloc k source in self clock mode. in order to operate reliably, care must be taken to select proper values for external loop filter components. figure 3. basic pll functional diagram the procedure described below can be used to calcul ate the resistance and capac itance values using typical values for k 1 , f 1 and i ch from table 18. first, the vco gain at the desired vco output frequency is approximated by: the phase detector relationship is given by: i ch is the current in tracking mode. the loop bandwidth f c should be chosen to fu lfill the gardner?s stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response. and finally the frequency relationship is defined as with the above inputs the re sistance can be calculated as: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: the stabilization delays shown in table 18 are de pendant on pll operationa l settings and external component selection (for example, crystal, xfc filter). phase detector 1 refdv+1 k f ref v dd pll r c p c s k v loop divider 1 synr+1 f vco f osc 1 2 f cmp vco ? k v k 1 e f 1 f vco ? () k 1 1v ? ------------------------- - ? = k i ch ? k v ? = f c 2 f ref ?? 1 2 + + () ? ---------------------------------------- - 1 50 ------ f c f ref 450 ? -------------- 0.9 = () ; < ?? ?? < n f vco f ref ----------- -2 synr 1 + () ? == r 2 nf c ??? k --------------------------- - = c s 2 2 ? f c r ?? --------------------- 0.516 f c r ? ------------- - 0.9 = () ; = c s 20 c p c s 10 ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.8.2.1 jitter information the basic functionality of the pll is shown in figure 3. with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly. the adjustment is done continuously with no abrupt changes in the cl ock output frequency. noise, voltage, temperature and other factors cause slight variations in the control lo op resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure 4. it is important to note that the pre-scaler used by timers and serial modules will eliminate the effect of pll jitter to a large extent. figure 4. jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n ). thus, jitter is defined as: for n < 100, the following equation is a good fit for the maximum jitter: figure 5. maximum bus clock jitter approximation 0 t min1 123n?1n t nom t max1 t min (n) t max (n) jn () max 1 t max n () nt nom ? --------------------- ?1 t min n () nt nom ? --------------------- ? , ?? ?? = jn () j 1 n -------- j 2 + = 01 5 10 20 15 n j(n) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
17 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.8.3 pll characteristics 3.8.4 crystal monitor time-out the time-out table 19 shows the delay for the crystal monito r to trigger when the clock stops, either at the high or at the low level. the corresponding clock period with an ideal 50% duty cycle is twice this time-out value. 3.8.5 clock quality checker the timing for the clock quality check is derive d from the oscillator and the vco frequency range in table 18. these numbers define th e upper time limit for the individu al check windows to complete. table 18. pll characteristics num c rating symbol min typ max unit j1 pll reference frequency, crystal oscillator range 1 1 v dd pll at 2.5 v. f ref 0.5 ? 16 mhz j2 p self clock mode frequency f scm 1?5.5mhz j3 d vco locking range f vco 8?40mhz j4 d lock detector transition from acquisition to tracking mode |? trk | 3?4% 2 2 percentage deviation from target frequency j5 d lock detection |? lock | 0?1.5% 2 j6 d un-lock detection |? unl | 0.5 ? 2.5 % 2 j7 d lock detector transition from tracking to acquisition mode |? unt | 6?8% 2 j8 c pllon total stabilization delay (auto mode) 3 3 pll stabilization delay is highly dependent on operationa l requirement and external component values (for example, crystal and xfc filter co mponent values). notes 4 and 5 show component values for a typical configurations. appropr iate xfc filter values shoul d be chosen based on operational requ irement of system. t stab ?0.5 4 4 f ref = 4 mhz, f sys = 25 mhz (refdv = 0x03, synr = 0x01), c s = 4.7 nf, c p = 470 pf, r s =10 k ? . 3 5 5 f ref = 4 mhz, f sys = 8 mhz (refdv = 0x00, synr = 0x01), c s = 33 nf, c p = 3.3 nf, r s = 2.7 k ? . ms j9 d pllon acquisition mode stabilization delay 3 t acq ?0.3 5 1 4 ms j10 d pllon tracking mode stabilization delay 3 t al ?0.2 5 2 4 ms j11 d charge pump current acquisition mode | i ch | ? 38.5 ? a j12 d charge pump current tracking mode | i ch | ?3.5? a j13 d jitter fit vco loop gain parameter k 1 ? ?100 ? mhz/v j14 d jitter fit vco loop frequency parameter f 1 ?60?mhz j15 c jitter fit parameter 1 j 1 ??tbd% 4 j16 c jitter fit parameter 2 j 2 ??tbd% 4 table 19. crystal monitor time-outs min typ max unit 61018.5 s table 20. crg maximum clock quality check timings clock check windows value unit check window 9.1 to 20.0 ms timeout window 0.46 to 1.0 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.8.6 startup table 21 summarizes several startup characteristic s explained in this section. refer to the mac7100 microcontroller family reference manual (mac7100rm/d) for a detailed description of the startup behavior. 3.8.6.1 power on and low vo ltage reset (por and lvr) the release level v porr and the assert level v pora are derived from the v dd 2.5 supply. the assert level v lvra is derived from the v dd 2.5 supply. they are also valid if th e device is powered externally. after releasing the por or lvr reset, the oscillator and th e clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self-generated clock. the fastest startup time possible is given by t uposc (refer to table 17). 3.8.6.2 sram data retention the sram contents integrity is guaranteed if the porf bit in th e crgflg register is not set following a reset operation. 3.8.6.3 external reset when external reset is asserted for a time greater than pw rstl , the crg module generates an internal reset and the cpu starts fetching the reset vector with out doing a clock quality check, if there was stable oscillation before reset. 3.8.6.4 stop recovery the mcu can be returned to run mode from the stop mode by an extern al interrupt. a clock quality check is performed in the same mann er as for por before releasing the clocks to the system. 3.8.6.5 pseudo stop and doze recovery recovery from pseudo stop and doze modes are essentially the same, sinc e the oscillator is not stopped in either mode. the controller is return ed to run mode by intern al or external interrupts or other wakeup events in the system. after t wrs , the cpu fetches an interrupt vector if the wakeup event was an interrupt, or continues to execute code if the wakeup event was not an interrupt. table 21. crg startup characteristics num c rating symbol min typ max unit k1 t por release level v porr ??2.07v k2 t por assert level v pora 0.97 ? ? v k3 d reset input pulse width, minimum input time pw rstl 2??t osc k4 d startup from reset n rst 192 ? 196 n osc k5 d interrupt pulse width, irq edge-sensitive mode pw irq 20 ? ? ns k6 d wait recovery startup time t wrs ??14t cyc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
19 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.9 external bus timing specifications table 22 lists processor bus input timings, whic h are shown in figure 6, figure 7 and figure 8. note all processor bus timings are synchronou s; that is, input setup/hold and output delay with respect to the risi ng edge of a reference clock. the reference clock is the clkout output. all other timing relationships ca n be derived from these values. figure 6. general input timing requirements table 22. external bus input timing specifications num c rating 1 1 timing specifications have been indicated taking into account the full drive strength for the pads. symbol min max unit l1 clkout t cyc 23 ? ns control inputs l2a control input valid to clkout high 2 2 ta pins are being referred to as control inputs. t cvch 13 ? ns l3a clkout high to control inputs invalid 2 t chcii 0?ns data inputs l4 data input (data[15:0]) valid to clkout high t divch 9?ns l5 clkout high to data input (data[15:0]) invalid t chdii 0?ns clkout(45mhz) 1.5 v 1.5 v valid invalid invalid t setup t hold input setup & hold input rise time v h = v ih v l = v il t rise = 1.5 ns input fall time v h = v ih v l = v il t fall = 1.5 ns clkout inputs 1.5 v l4 l5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.9.1 read and write bus cycles table 23 lists processor bus output timings. read/write bus timings listed in table 23 are shown in figure 7 and figure 8. table 23. external bus output timing specifications num c rating symbol min max unit control outputs l6a clkout high to chip selects valid 1 1 cs n transitions after the falling edge of clkout. t chcv ?0.5t cyc + 10 ns l6b clkout high to byte select (bs [1:0]) valid 2 2 bs n transitions after the falling edge of clkout. t chbv ?0.5t cyc + 10 ns l6c clkout high to output select (oe ) valid 3 3 oe transitions after the falling edge of clkout. t chov ?0.5t cyc + 10 ns l7a clkout high to control output (bs [1:0], oe ) invalid t chcoi 0.5t cyc + 2 ? ns l7b clkout high to chip selects invalid t chci 0.5t cyc + 2 ? ns address and attribute outputs l8 clkout high to address (addr[21:0]) and control (r/w) valid t chav ?10ns l9 clkout high to address (addr[21:0]) and control (r/w ) invalid t chai 2?ns data outputs l10 clkout high to data output (data[15:0]) valid t chdov ?13ns l11 clkout high to data output (data[15:0]) invalid t chdoi 2?ns l12 clkout high to data output (data[15:0]) high impedance t chdoz ?9ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
21 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics figure 7. read/write (internally terminated) bus timing clkout cs n addr[21:0] oe r/w bs [1:0] s0 s2 s1 s3 s4 s5 s0 s1 s2 s3 s4 s5 data[15:0] ta (h) l6a l7b l6a l7b l8 l8 l8 l9 l6c l7a l1 l9 l6b l6b l7a l7a l4 l5 l10 l11 l12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
22 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics figure 8. read bus cycle terminated by ta clkout cs n addr[21:0] oe r/w bs [1:0] s0 s2 s1 s3 s4 s5 s0 data[15:0] ta s1 l6a l7b l7a l7a l8 l9 l6c l6b l4 l5 l2a l3a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
23 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.10 analog-to-digital converter characteristics table 24 and table 25 show conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: v ss a v rl v in v rh v dd a. this constraint exists because the sample buffer amplifier cannot drive beyond the atd power supply levels. if the input level goes outside of this range it will effectively be clipped. 3.10.1 factors influencing accuracy three factors ? source resistance, source capacitance and current injection ? have an influence on the accuracy of the atd. table 24. atd operating characteristics in 5 v range conditions shown in table 6 unless otherwise noted num c rating symbol min typ max unit m1 d reference potential low high v rl v rh v ss a v dd a 2 ? ? v dd a 2 v dd a v v m2 c differential reference voltage 1 1 full accuracy is not guaranteed when differential voltage is less than 4.50 v v rh ? v rl 4.50 5.00 5.25 v m3 d atd clock frequency f atdclk 0.5 ? 2.0 mhz m4 d atd 10-bit conversion periodclock cycles 2 @ 2.0mhz f atdclk 2 minimum time assumes final sample period of 2 atd clocks; maximum time assumes final sample period of 16 atd clocks. n conv10 t conv10 14 7 ? ? 28 14 cycles s m5 d atd 8-bit conversion periodclock cycles 2 @ 2.0mhz f atdclk n conv8 t conv8 12 6 ? ? 26 13 cycles s m6 d recovery time (v dd a = 5.0 v) t rec ??20 s m7 p reference supply current 1 atd module enabled i ref ??0.375ma m8 p reference supply current 2 atd modules enabled i ref ??0.750ma table 25. atd operating characteristics in 3.3 v range conditions shown in table 6, with v dd x = 3.3 v 10% and a temperature maximum of +140 c unless otherwise noted. num c rating symbol min typ max unit n1 d reference potential low high v rl v rh v ss a v dd a 2 ? ? v dd a 2 v dd a v v n2 c differential reference voltage 1 1 full accuracy is not guaranteed when differential voltage is less than 3.0 v v rh ?v rl 3.0 3.3 3.6 v n3 d atd clock frequency f atdclk 0.5 ? 2.0 mhz n4 d atd 10-bit conversion periodclock cycles 2 conv, time at 2.0mhz atd clock f atdclk 2 minimum time assumes final sample period of 2 atd clocks; maximum time assumes final sample period of 16 atd clocks. n conv10 t conv10 14 7 ? ? 28 14 cycles s n5 d atd 8-bit conversion periodclock cycles 2 conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 ? ? 26 13 cycles s n6 d recovery time (v dd a=5.0 v) t rec ??20 s n7 p reference supply current 1 atd module enabled i ref ??0.375ma n8 p reference supply current 2 atd modules enabled i ref ??0.250ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
24 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.10.1.1 source resistance due to the input pin leakage current as specified in table 15 in conjunction with the source resistance there will be a voltage drop from the signal source to the at d input. the maximum specified source resistance r s , results in an error of less than 1/2 lsb (2.5 mv) at the maximum leakage current. if the device or operating conditions are less than the worst case, or leakage-induc ed errors are acceptable, larger values of source resistance are allowed. 3.10.1.2 source capacitance when sampling, an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the extern al capacitance and the pin capacitan ce. for a maximum sampling error of the input voltage 1 lsb, then the external filter cap acitor must be calculated as, c f 1024 (c ins ? c inn ) . 3.10.1.3 current injection there are two cases to consider: 1. a current is injected into the channel being converted. the channe l being stressed has conversion values of 0x3ff (0xff in 8-bit mode ) for analog inputs greater than v rh and 0x000 for values less than v rl unless the current is higher th an specified as disruptive condition. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as v err =k r s i inj , with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. table 26. atd electrical characteristics conditions are shown in table 6 unless otherwise noted num c rating symbol min typ max unit p1 c max input source resistance r s ?? 1k ? p2 t total input capacitance non sampling sampling c inn c ins ? ? ? ? 10 22 pf pf p3 c disruptive analog input current i na ?2.5 ? 2.5 ma p4 c coupling ratio positive current injection k p ??tbda/a p5 c coupling ratio negative current injection k n ??tbda/a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
25 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.10.2 atd accuracy table 27 and table 28 specify the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. for the following definitions see also figure 8. differential non-linearity (dnl) is defined as th e difference between two adjacent switching steps. the integral non-linearity (inl) is defined as the sum of all dnls: table 27. atd conversion performance in 5 v range conditions shown in table 6 unless otherwise noted. v ref = v rh ? v rl = 5.12 v, resulting in one 8 bit count = 20 mv and one 10 bit count = 5 mv f atdclk = 2.0 mhz, 4.5 v v dd a 5.5 v num c rating symbol min typ max unit q1 p 10-bit resolution lsb ? 5 ? mv q2 p 10-bit differential nonlinearity dnl ?1 ? 1 counts q3 p 10-bit integral nonlinearity inl ?2.5 1.5 2.5 counts q4 p 10-bit absolute error 1 1 these values include the quantization error which is inherently 1/2 count for any a/d converter. ae ?3 2.0 3 counts q5 p 8-bit resolution lsb ? 20 ? mv q6 p 8-bit differential nonlinearity dnl ?0.5 ? 0.5 counts q7 p 8-bit integral nonlinearity inl ?1.0 0.5 1.0 counts q8 p 8-bit absolute error 1 ae ?1.5 1.0 1.5 counts table 28. atd conversion performance in 3.3 v range conditions shown in table 6 unless otherwise noted. v ref = v rh ? v rl = 5.12 v, resulting in one 8 bit count = 20 mv and one 10 bit count = 5 mv f atdclk = 2.0 mhz, 4.5 v v dd a 5.5 v num c rating symbol min typ max unit r1 p 10-bit resolution lsb ? 3.25 ? mv r2 p 10-bit differential nonlinearity dnl ?1.5 ? 1.5 counts r3 p 10-bit integral nonlinearity inl ?3.5 1.5 3.5 counts r4 p 10-bit absolute error 1 1 these values include the quantization error which is inherently 1/2 count for any a/d converter. ae ?5 2.0 5 counts r5 p 8-bit resolution lsb ? 13 ? mv r6 p 8-bit differential nonlinearity dnl ?0.5 ? 0.5 counts r7 p 8-bit integral nonlinearity inl ?1.5 1.0 1.5 counts r8 p 8-bit absolute error 1 ae ?1.5 1.0 1.5 counts dnl i () v i v i1 ? ? 1 lsb ----------------------- 1 ? = inl n () dnl i () i1 = n v n v 0 ? 1 lsb ------------------- n ? == f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
26 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics figure 9. atd accuracy definitions note figure 8 shows only definitions, for sp ecification values refer to table 27. 0x3ff 0x3fe 0x3fd 0x3fc 0x3fb 0x3fa 0x3f9 0x3f8 0x3f7 0x3f6 0x3f5 0x3f4 0x3f3 9 8 7 6 5 4 3 2 1 0 0 10203040505055 5065 5075 5085 5095 5105 5115 5060 5070 5080 5090 5100 5110 5120 5 152535 1 2 0xfd 0xfe 0xff 10-bit absolute error boundary ideal transfer curve 8-bit transfer curve 10-bit transfer curve 8-bit absolute error boundary 10-bit resolution 8-bit resolution lsb dnl v i?1 v i v in mv f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
27 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.10.3 atd electrical specifications table 29 lists the dc electrical characteristics for the atd module. table 27 lists the analog-to-digital conversion performance specifications. table 29. atd electrical characteristics (operating) 1 1 all voltages referred to v ss a, ?40 to 125 o c, v dd a = 5.0 v 10% and 2.0 mhz conversion rate unless otherwise noted. refer to table 6 for additional operating conditions. num c rating symbol min typ max unit s1 s2 reference potential 2 low high 2 to obtain full-scale, full-range results, v ss a < v rl < v indc < v rh < v dd a. sample buffer amp cannot drive beyond the power supply levels. if the input level goes outs ide of this range, it will effectively be clipped. v rl v rh v ss a v dd a 2 ? ? v dd a 2 v dd a v v s3 voltage difference v rh ? v rl 3 3 full accuracy is not guaranteed when the differen tial reference voltage is less than 4.5 v. v rh ? v rl 4.5 ? 5.5 v s4 analog input voltage v indc ?0.3 ? v dd a + 0.3 v s5 s6 digital input voltage high low v ih v il 0.7 v dd a v ss a ? 0.3 ? ? v dd a + 0.3 0.2 v dd a v v s7 analog supply current run ?40 c 4 i dd a run ?tbdtbdma 25 c 4 ?tbdtbdma 85 c 4 4 85 c, 105 c, and 125 c refer to the "c", "v", and "m" temperature options, respectively. ?tbdtbdma 105 c 4 ?tbdtbdma 125 c 4 ?tbdtbdma s8 pseudo ?40 c 4 i dd a pseudo_stop ?tbdtbd a stop 25 c 4 ?17tbd a 85 c 4 ?tbdtbd a 105 c 4 ?tbdtbd a 125 c 4 ?tbdtbd a s9 stop ?40 c 4 i dd a stop ?tbdtbd a (low power) 25 c 4 ?17tbd a 85 c 4 ?tbdtbd a 105 c 4 ?tbdtbd a 125 c 4 ?tbdtbd a s10 reference supply current i ref ? 200 250 a s11 input injection current 5 5 the input injection current is specified to 1 count of error. i inj ?? 2ma s12 input current, off channel 6 i off ?200 ? 200 na s13 s14 total input capacitance not sampling sampling c inn c ins ? ? ? ? 10 15 pf pf s15 disruptive analog input current 7 i na ?3 ? 3 ma s16 coupling ratio 8 k??10 ?4 a/a s17 incremental error due to injection current (all channels with 10k < rs < 100k) 9 ?? 1 counts s18 incremental error due to injection current ( channel under test rs=10k, i inj = 3ma ) 9 ?? 1 counts s19 incremental capacitance during samplin g 10 c samp ?? 5pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
28 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.10.4 atd timing specifications 6 maximum leakage occurs at maximum operating temperat ure. current decreases by approximately one-half for each 8 to 12 c, in the ambient temperature range of 50 to 125 c. 7 below disruptive current conditions, the channel being stress ed has conversion values of 0x3ff for analog inputs greater than v rh and 0x000 for values less than v rl . this assumes that v dd a av rh and v rl v ss a due to the presence of the sample amplifier. other channel s are not affected by non -disruptive conditions. 8 coupling ratio, k, is defined as the ratio of the output current, i out , measured on the pin under test to the injection current, i inj , when both adjacent pins are overstressed with the specified injection current. k = i out i inj . the input voltage error on the channel under test is calculated as verr = i inj x k x r s . 9 total injection current is determined by the number of channels injecting (for example, 15), external injection voltage (v inj ?v posclamp , or v inj ? v negclamp ), and the external source impedance, rs, wherein all input channels have the same values. to determine the error voltage on the converted channel, only the two adjacent channels are expected to contribute to the error voltage: v errj = (v inj ? v clamp ) k 2. 10 for a maximum sampling erro r of the input voltage 1lsb, then the external filter capacitor, c f 1024 c samp . the value of c samp in the new design may be reduced, or increased slightly. table 30. atd performance specifications 1 1 all voltages referred to v ss a, v dd a = 5.0 v10%, atd clock = 2.1 mhz., ?40 to 125 c. num c rating symbol min typ max unit t1 d 10-bit resolution lsb ? 5 ? mv t2 d 10-bit differential nonlinearity 2 2 note: 1 lsb = 1 count (at v ref = 5.12 v, one 8 bit count = 20 mv, one 10-bit count = 5 mv) dnl ?1 ? 1 counts t3 d 10-bit integral nonlinearity 2 inl ?2 ? 2 counts t4 d 10-bit absolute error 2, 3 3 these values include quantization error which is inherently 1/2 count for any a/d converter. ae ?2.5 ? 2.5 counts t5 d max input source impedance 4 4 this value is based on error attributed to the specified leakage value of tbd na resulting in an error of less than 1/2 lsb (2.5 mv). if operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowable. r s ? ? 100 k ? table 31. atd timing specifications num c rating symbol min typ max unit u1 d atd module clock frequency f clk ??25.0mhz u2 d atd conversion clock frequency f atdclk 0.5 ? 2.0 mhz u3 d atd 10-bit conversion period * clock cycles conv. time n conv10 * t conv10 14 * 7 ? ? 28 * 14 cycles * sec u4 d stop recovery time (v dd a = 5.0 v) t sr ??100 sec table 32. atd external trigger timing specifications num c parameter symbol min max unit v1 d etrig minimum period t period ?1 sample + 1 conv. + 1 atd clock cycle v2 d etrig minimum pulse width t pw 2 ? sys clk v3 d etrig level recovery 1 1 time prior to end of conversion that the etrig pin mu st be deactivated so that a nother conversion sequence does not start. t lr 1 ? sys clk v4 d conversion start delay t dly ? 2 sys clk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
29 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics figure 10. atd external trigger timing diagram level sensitive low active t dly t dly max frequency t lr t dly sequence coversion activity complete flag low active sequence complete flag coversion activity level sensitive t pw falling edge active t dly t dly max frequency coversion activity edge sensitive t pw t period etrig adx etrig ascif adx etrig ascif adx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
30 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.11 serial peripheral interface electrical specifications 3.11.1 master mode figure 11 and figure 12 illustrate master mode timing. timing values are shown in table 33. 3.11.2 slave mode figure 13 and figure 14 illustrate the slave mode timing. timing values are shown in table 34. table 33. spi master mode timing characteristics 1 1 the numbers 7, 8 in the column labeled ?num? are mi ssing. this has been done on purpose to be consistent between the master and the slave timing shown in table 34. conditions are shown in table 6 unless otherwise noted, c load = 200pf on all outputs num c rating symbol min typ max unit w1a p operating frequency f op dc ? 1 / 4f bus w1b p sck period t sck = 1/f op t sck 4 ? 2048 t bus w2 d enable lead time t lead 1 / 2? ?t sck w3 d enable lag time t lag 1 / 2? ?t sck w4 d clock (sck) high or low time t wsck t bus ? 30 ? 1024 t bus ns w5 d data setup time (inputs) t su 25 ? ? ns w6 d data hold time (inputs) t hi 0??ns w9 d data valid (after enable edge) t v ??25ns w10 d data hold time (outputs) t ho 0??ns w11 d rise time inputs and outputs t r ??25ns w12 d fall time inputs and outputs t f ??25ns table 34. spi slave mode timing characteristics conditions are shown in table 6 unless otherwise noted, cload = 200pf on all outputs num c rating symbol min typ max unit x1a p operating frequency f op dc ? 1 / 4f bus x1b p sck period t sck = 1/f op t sck 4 ? 2048 t bus x2 d enable lead time t lead 1??t cyc x3 d enable lag time t lag 1??t cyc x4 d clock (sck) high or low time t wsck t cyc ? 30 ? ? ns x5 d data setup time (inputs) t su 25 ? ? ns x6 d data hold time (inputs) t hi 25 ? ? ns x7 d slave access time t a ?? 1t cyc x8 d slave sin disable time t dis ?? 1t cyc x9 d data valid (after sck edge) t v ??25ns x10 d data hold time (outputs) t ho 0??ns x11 d rise time inputs and outputs t r ??25ns x12 d fall time inputs and outputs t f ??25ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
31 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics figure 11. spi master timing (cpha = 0) figure 12. spi master timing (cpha =1) pcsx sck (cpol = 0) (output) sck (cpol = 1) (output) (output) msb in 2 msb out 2 bit 6 ... 1 sin (input) sout (output) lsb out lsb in bit 6 ... 1 1 if configured as output. 2 lsbfe = 0. for lsbfe = 1, bit order is lsb, bit 1, ..., bit 6, msb. w2 w1b w3 w4 w4 w12 w5 w6 w11 w9 w9 w10 pcsx sck (cpol = 0) (output) sck (cpol = 1) (output) (output) msb in 2 bit 6 ... 1 sin (input) sout (output) lsb in bit 6 ... 1 port data master msb out 2 port data master lsb out 1 if configured as output. 2 lsbf = 0. for lsbf = 1, bit orde r is lsb, bit 1, ..., bit 6, msb. w10 w9 w6 w11 w12 w11 w5 w4 w4 w2 w1b w3 w12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
32 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics figure 13. spi slave timing (cpha = 0) figure 14. spi slave timing (cpha =1) ss sck (cpol = 0) (input) sck (cpol = 1) (input) (input) sout (output) sin (input) slave msb out bit 6 ... 1 slave lsb out msb in lsb in bit 6 ... 1 x2 x1b x4 x4 x5 x6 x7 x8 x9 x10 x10 x12 x12 x11 x11 x3 ss sck (cpol = 0) (input) sck (cpol = 1) (input) (input) bit 6 ... 1 sout (output) sin (input) slave msb out slave lsb out msb in lsb in bit 6 ... 1 x2 x1b x4 x4 x5 x6 x7 x8 x9 x10 x12 x12 x11 x11 x3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.12 flexcan electrical specifications 3.13 program flash and data flash timing characteristics note unless otherwise noted the abbrevia tion nvm (non-volatile memory) is used for both program flash and data flash. 3.13.1 nvm timing the time base for all nvm program or erase operations is derived from the system clock divided by two (fsys/2). a minimum system frequency f nvmfsys is required for performing program or erase operations. the nvm modules do not have any me ans to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. atte mpting to program or erase the nvm modules at a lower frequency a full prog ram or erase transition is not assured. the flash and data flash program and erase operatio ns are timed using a clock derived from the system frequency using the cfmclkd register. the frequency of this clock must be set within the limits specified as f nvmop . the minimum program and erase times shown in table 36 are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2 mhz. 3.13.1.1 single word programming the programming time for single word programming is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated accord ing to the following formula. 3.13.1.2 burst programming this applies only to the flash wher e up to 32 words in a row can be programmed consecutively using burst programming by keeping the comman d pipeline filled. the time to pr ogram a consecutive word can be calculated as: the time to program a whole row is: burst programming is more than 2 times faster than single word programming. table 35. flexcan wake-up pulse characteristics conditions are shown in table 6 unless otherwise noted num c rating symbol min typ max unit y1 p flexcan wake-up dominant pulse filtered t wup ?? 2 s y2 p flexcan wake-up dominant pulse passed t wup 5?? s t swpgm 9 1 f nvmop ----------------- - ? 25 1 f bus -------- - ? + = t bwpgm 4 1 f nvmop ----------------- - ? 9 1 f bus -------- - ? + = t brpgm t swpgm 31 t bwpgm ? + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.13.1.3 sector erase erasing a 4k byte flash sector takes: the setup time can be ignored for this operation. 3.13.1.4 mass erase erasing a nvm block takes: the setup time can be ignored for this operation. 3.13.1.5 blank check the time it takes to perform a blank check on the flash or data flash is depend ant on the location of the first non-blank word starting at relative address zero. it takes one bus cycle per word to verify plus a setup of the command. table 36. nvm timing characteristics 1 1 conditions are shown in table 6 unless otherwise noted num c rating symbol min typ max unit z1 d system clock/2 f nvmfsys 0.5 ? 50 2 2 restrictions for oscillator in crystal mode apply! mhz z2 d bus frequency for programming or erase operations f nvmbus 1??mhz z3 d operating frequency f nvmop 150 ? 200 khz z4 p single word programming time t swpgm 46 3 3 minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequency f bus . ?74.5 4 4 maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus . refer to formulae in section 3.13. 1.1, ?single word programming,? through section 3.13.1.4, ?mass erase,? for more information. s z5 d flash burst programming consecutive word t bwpgm 20.4 3 ?31 4 s z6 d flash burst programming time for 32 words t brpgm 678.4 3 ? 1035.5 4 s z7 p sector erase time t era 20 5 5 minimum erase times are achieved under maximum nvm operating frequency f nvmop . ?26.7 4 ms z8 p mass erase time t mass 100 5 ? 133 4 ms z9 d blank check time flash per block t check 11 6 6 minimum time, if first word in the array is not blank ? 32778 7 7 maximum time to complete check on an erased block t cyc z10 d blank check time data flash per block t check 11 6 ?2058 7 t cyc t era 4000 1 f nvmop ----------------- - ? t mass 20000 1 f nvmop ----------------- - ? t check location t cyc 10 t cyc ? + ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
35 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice electrical characteristics 3.13.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen earl y life failures. the failure rates fo r data retention and program/erase cycling are specified at the oper ating conditions noted. the progra m/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. note all values shown in table 37 are target values and subject to characterization. for flash cycling performance, each program operation must be preceded by an erase. table 37. nvm reliability characteristics conditions shown in table 6 unless otherwise noted. num c rating min unit z10 c program/data flash program/erase endurance (?40c to +125c) 10,000 cycles z11 c program/data flash data retention lifetime 15 years f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
36 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice device pin assignments 4 device pin assignments the mac7100 family is available in 208-pin ball gr id array (map bga), 144-pin low profile quad flat (lqfp), 112-pin lqfp, and 100-pin lqfp package optio ns. the family of devices offer pin-compatible packaged devices to assist with system developmen t and accommodate a direct application enhancement path. refer to table 1 for a comparison of the pe ripheral sets and package options for each device. most pins perform two or more functions, which is described in more detail in the mac7100 microcontroller family reference manual (mac7100rm/d). figure 15, fi gure 16, figure 17, figure 18, and figure 19 show the pin assi gnments for the various packages. 4.1 mac7141pv pin assignments figure 15. pin assignments for mac7141 in 100-pin lqfp pg4 pg5 pg6 pg7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pf11 pf10 pf9 pf8 pf7 pb11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 mac7141 100 lqfp 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa7 pa8 pa9 v dd x v ss x pd4 pd3 clkout pb15 pb14 pb13 pb10 pb9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pg3 pg2 pg1 pg0 tms tck tdo tdi v dd 2.5 v ss 2.5 pd10 pd9 pd8 pd7 pd6 pe15 pe14 pe13 pe12 pe11 pe10 v ss a v rl v rh v dd a 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset v ss x v dd x pg12 pg13 v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test pa15 pd0 pd1 pb12 / / / / / / / / / / / / / / / / / / / / / / ss_a pcss_a v ss x v dd x n/c / / cntx_a cnrx_a cntx_b cnrx_b sda scl sin_a sout_a sck_a pcs0_a pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 emios11 emios10 emios9 emios8 emios7 / / / / / / / / / / / emios6 emios5 emios4 emios3 emios2 emios1 emios0 rxd_d txd_d modb moda nexpr nexps / / / pcs2_b / an9_a / an8_a / an7_a / an6_a / an5_a / an4_a / an3_a / an2_a / an1_a / an0_a / irq / xirq / sin_b / sout_b / sck_b / pcs5_b / pcs0_b / pcs1_b / rdy ' / mseo ' / mdo1' / mdo0' / evti ' / evto ' / mcko' / xclks / pcss_b / ss_b / txd_a / rxd_a / txd_b / rxd_b / an15_a / an14_a / an13_a / an12_a / an11_a / an10_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
37 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice device pin assignments 4.2 mac7121pv pin assignments figure 16. pin assignments for mac7121 in 112-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 pg4 pg5 pg8 pg9 pg10 pg11 pg6 pg7 v ss x v dd x pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pf11 pf10 pf9 pf8 mac7121 112 lqfp 28 pf7 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa7 pa8 pa9 pa10 pa11 pa12 pd5 pc15 v dd x v ss x pd4 pd3 clkout pb15 pb14 pb13 pb12 57 pb11 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 pg3 pg2 pg1 pg0 pg15 pg14 pa0 tms tck tdo tdi v dd 2.5 v ss 2.5 pd10 pd9 pd8 pd7 pd6 pe15 pe14 pe13 pe12 pe11 pe10 v ss a v rl v rh 85 v dd a 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset v ss x v dd x pg12 pg13 v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test pa15 pa14 pa13 pd0 pd1 56 pb9 / / / / / / / / / / / / / / / / / / / / / / / / / / cntx_a cnrx_a cntx_c cnrx_c cntx_d cnrx_d cntx_b cnrx_b sda scl sin_a sout_a sck_a pcs0 pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 emios11 emios10 emios9 emios8 emios7 ss_a pcss_a / / / / / / / / / / / / / / nexpr nexps ss_b emios6 emios5 emios4 emios3 emios2 emios1 emios0 rxd_d txd_d modb moda pcs0_b / / / an9_a an8_a an7_a an6_a an5_a an4_a an3_a an2_a an1_a an0_a irq xirq sin_b sout_b sck_b pcs1_b pcs2_b / / / / / / / / / / / / / / / / / / rdy ' / mseo ' / mdo1' / mdo0' / evti ' / evto ' / mcko' / xclks / txd_a / rxd_a / txd_b / rxd_b / txd_c / rxd_c / an15_a / an14_a / an13_a / an12_a / an11_a / an10_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
38 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice device pin assignments 4.3 mac7101pv pin assignments figure 17. pin assignments for mac7101 in 144-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pg4 pg5 pg8 pg9 pg10 pg11 pg6 pg7 pc0 pc1 pc2 pc3 v ss x v dd x pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pc4 pc5 pc6 pc7 pf11 pf10 pf9 pf8 pf7 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 mac7101 144 lqfp cntx_a cnrx_a cntx_c cnrx_c cntx_d cnrx_d cntx_b cnrx_b sda scl sin_a sout_a sck_a pcs0_a pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 emios11 emios10 emios9 emios8 emios7 ss_a pcss_a / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / pf6 pf5 pf4 pf3 pf2 pf1 pf0 pc8 pc9 pc10 pc11 pg12 pg13 pa15 pa14 pa13 pd11 pd12 pd0 pd1 pb9 reset v ss x v dd x v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test v ss x v dd x emios6 emios5 emios4 emios3 emios2 emios1 emios0 rxd_d txd_d modb moda pcs0_b nexpr nexps ss_b / / / / / / / / / / / / / / / ph10 pe9 ph9 pe8 ph8 pe7 ph7 pe6 ph6 pe5 ph5 pe4 ph4 pe3 ph3 pe2 ph2 pe1 ph1 pe0 ph0 v dd x v ss x pd15 pd14 pd13 pd4 pd3 clkout v ss x pb15 pb14 pb13 pb12 pb11 pb10 / an10_b / an9_a / an9_b / an8_a / an8_b / an7_a / an7_b / an6_a / an6_b / an5_a / an5_b / an4_a / an4_b / an3_a / an3_b / an2_a / an2_b / an1_a / an1_b / an0_a / an0_b / irq / xirq / sin_b / sout_b / sck_b / pcs1_b / pcs2_b / pcs5_b / rdy ' / mseo ' / mdo1' / mdo0' / evti ' / evto ' / mcko' / xclks / pcss_b / txd_a / rxd_a / txd_b / rxd_b / txd_c / rxd_c / / / / / / / tms tck tdo tdi v dd 2.5 v ss 2.5 v ss x v dd x / an15_a / an15_b / an14_a / an14_b / an13_a / an13_b / an12_a / an12_b / an11_a / an11_b / an10_a v ss a v rl v rh v dd a pg3 pg2 pg1 pg0 pg15 pg14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pe15 ph15 pe14 ph14 pe13 ph13 pe12 ph12 pe11 ph11 pe10 mcko evto evti mdo0 mdo1 mseo rdy f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
39 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice device pin assignments 4.4 mac7111pv pin assignments figure 18. pin assignments for mac7111 in 144-pin lqfp pf6 pf5 pf4 pf3 pf2 pf1 pf0 pc8 pc9 pc10 pc11 pg12 pg13 pa15 pa14 pa13 pd11 pd12 pd0 pd1 pb9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 pa7 pa8 pa9 pa10 pa11 pa12 pd5 pc15 pc14 pc13 pc12 v dd x v ss x pd15 pd14 pd13 pd4 pd3 clkout ta pb15 pb14 pb13 pb12 pb11 pb10 pg4 pg5 pg8 pg9 pg10 pg11 pg6 pg7 pc0 pc1 pc2 pc3 v ss x v dd x pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pf15 pf14 pf13 pf12 pc4 pc5 pc6 pc7 pf11 pf10 pf9 pf8 pf7 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 reset v ss x v dd x v dd 2.5 v ss 2.5 v ss r v dd r v dd pll xfc v ss pll extal xtal test v ss x v dd x mac7111 144 lqfp / txd_a / rxd_a / txd_b / rxd_b / txd_c / rxd_c / data0 / data1 / data2 / data3 / data4 / data5 / data6 tms tck tdo tdi v dd 2.5 v ss 2.5 v ss x v dd x / addr21 / addr20 / addr19 / addr18 / addr17 / an15_a / an14_a / an13_a / an12_a / an11_a / an10_a v ss a v rl v rh v dd a cntx_a cnrx_a cntx_c cnrx_c cntx_d cnrx_d cntx_b cnrx_b addr0 addr1 addr2 addr3 sda scl sin_a sout_a sck_a pcs0_a pcs1_a pcs2_a pcs5_a emios15 emios14 emios13 emios12 addr4 addr5 addr6 addr7 emios11 emios10 emios9 emios8 emios7 ss_a pcss_a / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / emios6 emios5 emios4 emios3 emios2 emios1 emios0 addr8 addr9 addr10 addr11 rxd_d txd_d data15 data14 data13 oe cs2 bs0 bs1 pcs0_b nexpr nexps modb moda ss_b / / / / / / / / / / / / / / / / / / / / / / / / / an9_a / an8_a / an7_a / an6_a / an5_a / an4_a / an3_a / an2_a / an1_a / an0_a / data7 / data8 / data9 / data10 / data11 / data12 / addr16 / addr15 / addr14 / addr13 / addr12 / r/w / cs0 / cs1 / irq / xirq / sin_b / sout_b / sck_b / pcs1_b / pcs2_b / pcs5_b / rdy ' / mseo ' / mdo1' / mdo0' / evti ' / evto ' / mcko' / xclks / pcss_b pg3 pg2 pg1 pg0 pg15 pg14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pd10 pd9 pd8 pd7 pd6 pe15 pe14 pe13 pe12 pe11 pe10 / mcko / evto / evti / mdo0 / mdo1 / mseo / rdy f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
40 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice device pin assignments 4.5 mac7131vf pin assignments 12345678910111213141516 a v ss xv ss x pg0 pg14 pa2 pa5 tclk tdi pe15 pe14 ph14 pe12 ph11 v rl v rh v dd a b v ss xv ss x pg2 pg15 pa0 pa4 tms tdo pd9 ph15 pe13 ph12 pe10 ph9 v dd aph8 c pg5 pg3 v ss x pg1 pa1 pa3 pa6 v ss 2.5 v dd x pd6 ph13 pe11 v dd a pe8 pe7 ph7 d pg9 pg8 pg4 v ss xv ss xv ss 2.5 v ss 2.5 pd10 pd8 pd7 v ss av ss a ph10 pe9 pe6 ph6 e pg6 pg11 pg10 v ss x pe4 pe5 ph5 ph4 f pc0 pg7 pc1 v ss x pe2 pe3 ph3 ph2 g pb0 pc2 pc3 v ss xv ss xv ss xv ss xv ss x ph0 ph1 pe1 pe0 h pb3 pb2 pb1 v dd xv ss xv ss xv ss xv ss x pa8 pa9 pa7 pa10 j pb5 pb6 pb4 v ss xv ss xv ss xv ss xv ss x pd5 pa12 pa11 pc15 k pb7 pb8 pf15 v ss xv ss xv ss xv ss xv ss x pc13 pc12 pc14 v dd x l pf14 pf13 pc4 v ss x pd13 pd14 pd15 pd4 m pf12 pc5 pc6 v ss xv ss xta pd3 clkout n pf11 pf10 pc7 v ss xv ss rv ss rv ss 2.5 v ss 2.5 v ss pll v ss pll v ss xv ss xv ss x pb11 pb14 pb15 p pf9 pf8 v ss xpf5 pc8pc10v dd xv ss 2.5 v dd rv dd x pa15 pd11 pd12 v ss x pb12 pb13 r pf7 v ss x pf6 pf3 pf1 pc9 pg12 pg13 v ss xv ss x test pa13 pd1 pb10 v ss xv ss x t v ss xv ss x pf4 pf2 pf0 pc11 reset v ss pll xfc extal xtal pa14 pd0 pb9 v ss xv ss x figure 19. pin assignments for mac7131 in 208-pin map bga f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
41 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice mechanical information 5 mechanical information 5.1 100-pin lqfp package figure 20. 100-pin lqfp mechani cal dimensions (case no. 983) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b-b 61 60 detail a l 41 40 80 -a- l -d- a s a-b m 0.20 d s h 0.05 a-b s 120 21 -b- b v j f n d view rotated 90 detail a b b p -a-,-b-,-d- e h g m m detail c seating plane -c- c datum plane 0.10 -h- datum plane -h- u t r q k w x detail c dim min max millimeters a 13.90 14.10 b 13.90 14.10 c 2.15 2.45 d 0.22 0.38 e 2.00 2.40 f 0.22 0.33 g 0.65 bsc h --- 0.25 j 0.13 0.23 k 0.65 0.95 l 12.35 ref m 5 10 n 0.13 0.17 p 0.325 bsc q 0 7 r 0.13 0.30 s 16.95 17.45 t 0.13 --- u 0 --- v 16.95 17.45 w 0.35 0.45 x 1.6 ref s a-b m 0.20 d s c s a-b m 0.20 d s h 0.05 d s a-b m 0.20 d s c s a-b m 0.20 d s c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
42 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice mechanical information 5.2 112-pin lqfp package figure 21. 112-pin lqfp mechanical dimensions (case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 2 0.050 seating plane gage plane 1 view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include 8 3 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
43 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice mechanical information 5.3 144-pin lqfp package figure 22. 144-pin lqfp mechani cal dimensions (case no. 918) n 0.20 t l-m 144 gage plane 73 109 37 seating 108 1 36 72 plane 4x 4x 36 tips pin 1 ident view y b b1 v1 a1 s1 v p g a s 0.1 c 2 view ab j1 j1 140x 4x view y plating f aa j d base metal section j1-j1 (rotated 90 ) 144 pl n 0.08 m tl-m dim a min max 20.00 bsc millimeters a1 10.00 bsc b 20.00 bsc b1 10.00 bsc c 1.40 1.60 c1 0.05 0.15 c2 1.35 1.45 d 0.17 0.27 e 0.45 0.75 f 0.17 0.23 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.13 0.20 r2 0.13 0.20 s 22.00 bsc s1 11.00 bsc v 22.00 bsc v1 11.00 bsc y 0.25 ref z 1.00 ref aa 0.09 0.16 0 0 7 11 13 1 2 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m, n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 6. dimension d does not include dambar protrusion. allwable dambar protrusion shall not cause the d dimension to exceed 0.35. 0.05 c l (z) r2 e c2 (y) r1 (k) c1 1 0.25 view ab n 0.20 t l-m m l n 2 t t 144x x x=l, m or n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
44 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice mechanical information 5.4 208-pin map bga package figure 23. 208-pin map bga mechani cal dimensions (case no. 1159a-01) k m m e d 0.2 4x x laser mark for pin a1 identification in this area a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15x e x s 0.3 m y xz 0.1 m z 208x b 3 metalized mark for pin a1 identification in this area 15x e s view m m view k (rotated 90? clockwise) 0.2 z 5 0.2 208 x z z 4 a a1 a2 dim min max millimeters a --- 2.00 a1 0.40 0.60 a2 1.00 1.30 b 0.50 0.70 d 17.00 bsc e 17.00 bsc e 1.00 bsc s 0.50 bsc notes: 1. 2. 3. 4. 5. all dimensions are in millimeters. interpret dimensions and tolerances per asme y14.5m, 1994. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. datum z (seating plane) is defined by the spherical crowns of the solder balls. parallelism measement shall exclude any effect of mark on top surface of package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
45 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice mechanical information this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mac7100ec/d , rev. 0.1, how to reach us: usa / europe / locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo, 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or in tegrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assu me any liability arising out of the application or use of any product or circuit, and specifica lly disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications c an and do vary in different applications and actual performance may vary over time. all operati ng parameters, including ?typicals? must be validated for each customer application by cust omer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications in tended to support or sustain life, or for any other application in which the failure of the motoro la product could create a situation where personal injury or death may occur. should buyer purc hase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distri butors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such un intended or unauthorized use, even if such claim alleges that motorola was negligent regardi ng the design or manufacture of the part. motorola and the stylized m logo are register ed in the u.s. patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mac7100ec/d , rev. 0.1, how to reach us: usa / europe / locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo, 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or in tegrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assu me any liability arising out of the application or use of any product or circuit, and specifica lly disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications c an and do vary in different applications and actual performance may vary over time. all operati ng parameters, including ?typicals? must be validated for each customer application by cust omer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications in tended to support or sustain life, or for any other application in which the failure of the motoro la product could create a situation where personal injury or death may occur. should buyer purc hase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distri butors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such un intended or unauthorized use, even if such claim alleges that motorola was negligent regardi ng the design or manufacture of the part. motorola and the stylized m logo are register ed in the u.s. patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
48 mac7100 microcontroller family hardware specifications motorola preliminary?subject to change without notice mechanical information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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